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Switch mode regulators
5 i6 k p( I l$ F' A1 zQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
1 Y) t# R1 w0 creceive power from VBAT or VCHG under application software control.- U: q e5 F2 \
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040: H1 k8 _2 R$ _; G
VFBGA and the flash memory. The System SMPS can supply power to external components.2 X: d" H8 h: D7 f$ j
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches. U* @6 d0 Q' a0 }
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
# U2 \9 X# O" R4 h; YThe SMPS both have three operating modes:9 n2 H$ w$ c& H& {: I! Y C
■ Normal (PWM)
1 m2 U* P$ T( d3 B0 V( u6 a■ Two low-power modes with reduced current capability:6 x+ _# R, E4 ~9 g) u
□ PFM
+ b9 j( q! `9 t: B# `5 C4 |1 U□ ULP
3 E* q: l& b2 E4 y4 cNormally the system auto switches, but this is optionally disabled.
$ D/ T1 r. t4 _5 }: Q$ SThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
2 \$ \+ x3 y$ m" l! x+ uFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-7 J& b2 f1 X8 J2 z
CH285-1).; Q) L/ k; I0 y2 A% i# S
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
2 u. M7 z; t, F' h0 Ja 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.1 E1 S O9 Y. a# u1 [+ w2 p
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
, N* v6 o6 j1 c. K1 C) n- A3 ~, d/ H% D& ^- X
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