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This application note is intended to provide recommendations concerning incorporation of circuit
6 O, H5 S; n8 J8 p. F8 cprotection devices and PCB layout guidelines to enhance an application's immunity in electrically noisy
# k/ s5 ?1 w- E: G3 A8 ` {* K Benvironments and survivability of EMI, EMC, EFT, and ESD events as described in the International
; H( M( X5 c1 F' }Electrotechnical Commission (IEC) standards: IEC 61000-4-2, IEC 61000-4-4, and IEC 61000-4-5.* v- }8 S4 V- O9 l( g
We will begin with:
! z B! |+ @: U& i+ q& A. c1. A brief review of EMI, EFT, and ESD specifications.1 t/ H0 `. @7 b( M$ S$ e: A
2. Key ESD protection device specifications definitions.
& s+ H$ _( B' I" @, [1 u3. A quick summary of EMI, EFT, and ESD protection strategies.6 D$ s- _) f8 k$ o
4. Capacitor filter selection and characteristics.7 f% }& o" L e6 x# W ?+ A8 V
5. PCB Hardware design best practices and layout considerations checklists:: S/ O) V+ Z+ X9 l; n5 Z
– Standard PCB design/layout practices
, }, `, S* k2 ?' @$ z: T4 a– Special Ethernet layout considerations
- F5 a. x4 _& R6 Y& d/ T– Special DDR Layout considerations
$ H7 S3 X& @( L/ H( ?5 p* `6. Software protection techniques.
5 @ n6 |2 C( }/ z; N7. Microcontroller reference circuit schematics with protection examples:6 V$ G. }( K" M- F
– RS-2322 a6 [' ~4 m1 r6 X6 s
– USB
2 Z8 j/ r' U; z3 q, M* J; M# ^– CAN FD and LIN
) R1 ?9 \. Z8 e0 H– Ethernet
# D1 W7 n5 k( t- o+ j6 b– Audio and mechanical switches) }: x* e5 H' `
– LCD
+ |$ t2 A8 h5 W. h– Power supplies
7 S% R' O! ]1 d( r# M2 M5 V– Reset and ICSP programming interface
1 D7 Y- O" K5 \3 i( g– SD memory card8 B, L% w9 I+ {2 h) ^) V
– I2C# N* q4 i! l" B4 O$ k
Reference Designs Note:
: U% u* P- V. N: PCost pressure is a constant consideration in any design. All of the circuit components in support of the; j- v, ~1 v, _! ?1 M
CPU were selected based on the lowest cost and availability, which met the threat protection
$ T' k6 y: p, erequirements. A user should carefully consider any substitutions. It is also highly recommended that the" Y; s0 V: y1 J& y
user consider designing in the protection elements in their layout, and then depopulate with zero ohm1 H6 s0 B; T2 o* \" P9 f
resistors as they think necessary, based on ESD, EMI, and EFT prototype board testing. This will save
5 }% y' ?) G+ {4 u- _4 U9 Asignificant board redesign time to market in the final product. |
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