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Switch mode regulators4 \$ T5 e. i0 g. l8 I
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
# _5 t" `+ i# wreceive power from VBAT or VCHG under application software control.# ^3 T$ V3 h$ D# G4 U' n
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040: X _* ?+ U1 F; l7 n: K
VFBGA and the flash memory. The System SMPS can supply power to external components.
% k% X3 ~) N$ E1 `: vThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
. e* Q3 b5 F4 qbetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
2 K% G4 u! w! qThe SMPS both have three operating modes:
4 [& {: Q, N# a: a1 _■ Normal (PWM)1 U6 F2 u1 k/ M7 q- M% y: a8 i
■ Two low-power modes with reduced current capability:
M! C9 s% [. h. H- P" T. o□ PFM
2 }2 ]9 ~' p C: Z1 h9 J□ ULP
+ T H. G2 K* H! P! PNormally the system auto switches, but this is optionally disabled.
/ ^% X# ]; C9 ^' B( ^& E- zThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
& `! ?3 k- N( m* ]. TFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
8 M9 b) ]2 o, K$ L2 }& g( LCH285-1).( J5 N" E" B! o( a3 u
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
9 I _) ]! K' q# M! q+ Ha 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
, N8 J4 w6 w& {6 i1 TThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.7 [/ c) X$ h5 f
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