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Switch mode regulators
8 ^) ?9 m. Y1 `% ]! l8 _: zQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
: t1 f" l7 E. ^( g$ \! ~/ r" treceive power from VBAT or VCHG under application software control.# u8 j2 \' m9 l: v
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040( _8 i& F/ X" o# h" Y
VFBGA and the flash memory. The System SMPS can supply power to external components.
; R, y& z$ R, L- SThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches$ f* l- G8 b- o! W' i) C7 c
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes./ B* R. q& q m! u i/ C
The SMPS both have three operating modes:
$ N' ~0 Y$ b. Z7 {■ Normal (PWM)
; P& R2 Z% J7 Y, d. N# ] J■ Two low-power modes with reduced current capability:
% q+ q2 l' ~( k# j o□ PFM+ }1 u+ O. @4 H# S, h
□ ULP8 ~4 q) g; G6 w0 q! p- W
Normally the system auto switches, but this is optionally disabled.
* Y; q5 p. @- S' AThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.7 i' Y5 _" }; s( ^8 \8 [
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-' E2 b- \+ W3 V
CH285-1).
7 Y. j( d: _9 x3 sA single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have4 l/ q& j; ~2 U* Q, \/ \9 v
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
+ w$ c/ |0 w3 t6 T4 S3 NThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.8 \8 K+ O# Y' j1 t1 O
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