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This application note is intended to provide recommendations concerning incorporation of circuit
- E; f1 P* H, P) v: {& } Yprotection devices and PCB layout guidelines to enhance an application's immunity in electrically noisy
' a9 \: I% N0 `5 xenvironments and survivability of EMI, EMC, EFT, and ESD events as described in the International
3 G6 M3 G8 O$ b# S2 W( i! Q& gElectrotechnical Commission (IEC) standards: IEC 61000-4-2, IEC 61000-4-4, and IEC 61000-4-5.3 m6 {. c& s9 O4 X% T& {0 l
We will begin with:+ @2 E$ W6 T! a7 @4 g" K9 |
1. A brief review of EMI, EFT, and ESD specifications.
: t& C" I( \0 X8 P- ]4 k2. Key ESD protection device specifications definitions.
- I, D' R, R" ?# w2 B9 [3. A quick summary of EMI, EFT, and ESD protection strategies.
& L7 Q. Y! P+ ~% ? @9 ]4. Capacitor filter selection and characteristics.
# l$ \# P. D2 Z2 |: I6 X5. PCB Hardware design best practices and layout considerations checklists:
) D- y8 P7 ^0 ]9 D– Standard PCB design/layout practices
, c& r% C) ?( ~8 n– Special Ethernet layout considerations
* r: V4 _# Q& U0 |2 K. u5 F– Special DDR Layout considerations
) r, r& E1 r+ A/ w4 X8 V3 L( o! J# W6. Software protection techniques.0 K" M8 x8 Z! a
7. Microcontroller reference circuit schematics with protection examples:4 K2 d7 {8 z4 x6 b7 q, b9 K/ x# g
– RS-232) R) }; R( i1 ?
– USB
5 ]; E+ Q% K5 Z( {: C0 p– CAN FD and LIN
3 x t: m( ^$ n0 \5 l– Ethernet" T( B: U/ I$ d0 f4 S
– Audio and mechanical switches5 b3 v2 n5 ]4 r8 z
– LCD
( F% `2 _" B; a+ x \– Power supplies. J( M; o/ V- M5 h) n0 l
– Reset and ICSP programming interface
& x. v1 b9 w, a9 i! M– SD memory card
2 Y' r9 t# @9 R– I2C
6 Z9 l, ~2 P% _, ~! k7 OReference Designs Note:
+ |+ R2 P2 W. B( zCost pressure is a constant consideration in any design. All of the circuit components in support of the% h4 d! m5 w* S! ^
CPU were selected based on the lowest cost and availability, which met the threat protection
/ G% U# X, c6 d, X4 a5 q+ n5 nrequirements. A user should carefully consider any substitutions. It is also highly recommended that the, L4 A e" _- i: G( s9 ^. O5 v
user consider designing in the protection elements in their layout, and then depopulate with zero ohm
3 [. U5 u& @5 s4 v7 Bresistors as they think necessary, based on ESD, EMI, and EFT prototype board testing. This will save3 q1 `* a( `. }8 t# @$ P8 |* B) h
significant board redesign time to market in the final product. |
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