IP核的使用有什么要求嗎

張翔10

剛接觸Verilog不久，需要做個FPGA解二階微分方程。
我用歐拉法解得，但調(diào)用IP核總是出毛病
比如
  d- W' K: ?+ _# W2 F* a- f& ?Error (10170): Verilog HDL syntax error at Eeler.v(22) near text "add_sub_inst";  expecting "<=", or "="
Error (10149): Verilog HDL Declaration error at Eeler.v(25): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(26): identifier "add_sub_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(27): identifier "mult_inst" is already declared in the present scope
; g4 m! b5 M8 |& cError (10149): Verilog HDL Declaration error at Eeler.v(28): identifier "add_sub_inst" is already declared in the present scope
Error (10170): Verilog HDL syntax error at Eeler.v(30) near text "$display";  expecting "endmodule"
Error (10759): Verilog HDL error at Eeler.v(30): object x declared in a list of port declarations cannot be redeclared within the module body
1 ]& K+ w$ ?$ m. X6 z) ~. CError (10759): Verilog HDL error at Eeler.v(30): object y declared in a list of port declarations cannot be redeclared within the module body
) V$ T2 ~" g* M# W' WError (10759): Verilog HDL error at Eeler.v(30): object z declared in a list of port declarations cannot be redeclared within the module body
Error (10170): Verilog HDL syntax error at Eeler.v(30) near text ")";  expecting ";"
Error (10112): Ignored design unit "Eeler" at Eeler.v(1) due to previous errors
. |, [/ O0 `2 D8 U6 t" U/ E# l) K編的源程序這樣
module Euler
(
input wire           clk,
" o- \9 ^5 ]& S0 X" A% K% b* X. Xinput wire    [31:0]   x,      //定義輸入量，單精度32位浮點數(shù)
# x3 e; k* O- n. c# rinput wire    [31:0]   y,
% i, _# t5 e$ minput wire    [31:0]   z,
input wire    [31:0]   h,
output wire    n1
+ j3 T2 h- c- B5 x2 F3 c);

1 x7 v& d8 r3 ^  R: Z$ u# A8 z
( X% |# d! d! S) ]4 ~% |- j# d0 T

1 e5 z  X! z- j' k. M" ?1 areg[31:0] z11;
2 G- g! q$ u! F- breg[31:0] z1;
: Q* H1 v" [: p& Qreg[31:0] y11;
reg[31:0] y12;
: q) Q2 }$ }6 |integer n;
7 d5 I; v  s- w! {" i2 H. h
, g' W  x+ h9 z) [1 H3 E* G
initial
//開始迭代
for (n = 0; n < 10; n=n+1)      
7 A( u! j. L" z& O- Ladd_sub add_sub_inst( .clock ( clk),  .dataa ( x ),.datab ( h ),.result ( x ));
' v, g5 @: v. _, A0 R) D5 K$ ^: ?! x4 h  nmult mult_inst( .clock ( clk ),  .dataa ( x),.datab ( z ),.result ( z11 ));            
* E5 ~8 z1 I- ]6 W0 b& fadd_sub add_sub_inst( .clock ( clk),  .dataa ( z11 ),.datab ( y ),.result ( z1 ) );      
$ S. F% F8 K9 g' M8 i- n9 I3 dmult mult_inst( .clock ( clk ),  .dataa ( h),.datab ( z),.result ( y11 ) );         
3 _; P/ I$ G2 t" A# j! ~add_sub add_sub_inst( .clock ( clk),  .dataa ( y ),.datab ( y11 ),.result ( y ) );   
6 A- N" A" d" i0 E; V+ N' ^mult mult_inst( .clock ( clk ),  .dataa (h),.datab ( z1 ),.result ( z12 ));         
+ x5 C; ~/ b! k, x8 zadd_sub add_sub_inst( .clock ( clk),  .dataa ( z ),.datab ( z12 ),.result ( z ) );
; Q5 [6 r% a; D. \% R8 D" x5 [  q

$display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
6 Q9 E9 z! c& o9 g5 f$ F# k* |" ?endmodule
, Y# Q, M5 m3 d想問一下，是IP調(diào)用有問題嗎？還是IP核不能在循環(huán)或函數(shù)里調(diào)用

xiaozhubanna

用另一種方式也有問題
5 @  ~0 A7 k% F" D7 R7 X0 Amodule Euler
(
input wire           clk,
input wire    [31:0]   x,      //定義輸入量，單精度32位浮點數(shù)
  Q' }) D7 V3 Einput wire    [31:0]   y,
) |5 @; f, o8 G) Y. D8 c' S0 Rinput wire    [31:0]   z,
input wire    [31:0]   h,
output wire    n1
7 A  r# [4 f4 w4 S" _9 Q3 K);


function   [31:0]   g;//加法器函數(shù)
  input   reg   [31:0]   x;
  input   reg   [31:0]   y;
1 y) _* K1 z& Z' x4 f          reg   [31:0]   z;  
begin         
add_sub add_sub_inst(
   //調(diào)用浮點數(shù)加法IP
.clock ( clk),
$ v) E- m5 Z" Y0 n+ N0 @" r.dataa ( x ),
- P1 ?8 f& \7 C/ f.datab ( y ),
2 E7 Y! J4 b) c& w.result ( z )
( ~' X3 I! j+ ?. R1 `8 d* ?    );
+ V5 w" V2 K. Y! m7 u' J6 ^    g    =    z;
end
0 H% C; ~: Y2 e5 xendfunction
9 B& D) R; g- }9 z8 M5 Y! d# ]
" ]) D9 h# J% ^+ S4 h) c8 |3 F

5 X% E8 n: T) N5 v
function[31:0]f;       //乘法器函數(shù)
4 e+ K2 o$ M9 x  input reg [31:0]x;
* E+ y) a4 D& a+ [  input reg [31:0]y;
. Q. L: j$ N+ a2 I4 R   reg [31:0]z;
begin   
' v* E2 W  r2 Bmult mult_inst(
  //調(diào)用浮點數(shù)乘法IP
1 @! _* Y* U0 C.clock ( clk ),
( w: F/ d1 Q" m4 C+ B! u; i.dataa ( x),
.datab ( y ),
.result ( z )
);
9 {* j) R. V4 z, J# d  f = z;
8 T  c7 u( N$ y end
- O3 @! I4 o# b: z1 q! ?endfunction
7 l( ^- S& p) ?, x* O4 P. v; M
% p: Z; y9 V; T( E9 n: X; ^: S% o
- ^& L7 T2 I2 e. d6 @8 K6 jreg[31:0] z11;
reg[31:0] z1;
) g2 p6 Q; B* Q4 P% q: T7 P$ Z& ~reg[31:0] y11;
reg[31:0] y12;
integer n;
" m: }+ z% X; G. e
' ?+ K, ~  V5 l7 i
, d/ p4 A( l2 K6 Q: H; x3 h3 Einitial
2 b- E* Z3 [: ^% n9 E% @' D2 dbegin
& T+ p) t- C- ]! l; ~: Y; |                     //開始迭代
$ `. T8 O$ e+ S7 S  Wfor (n = 0; n < 10; n=n+1)
      begin
5 W/ a# @/ z4 `+ J+ V5 h        x   = g(x,h);
        z11 = f(x,z);
        z1  = g(z11,y);
, x1 d! ]* y! m  C& ]  U        y11 = f(h,z);
5 C$ T0 w  g- `7 D! l7 B        y   = g(y,y11);
        z12 = f(h,z1);
        z   = g(z,z12);
/ @, u3 c4 h$ M9 J& n- K1 B       $display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
      end
end
endmodule
錯誤報告是
Error (10170): Verilog HDL syntax error at Eeler.v(16) near text "(";  expecting ";"
Error (10170): Verilog HDL syntax error at Eeler.v(33) near text "(";  expecting ";"
Error (10112): Ignored design unit "Euler" at Eeler.v(1) due to previous errors