電子產(chǎn)業(yè)一站式賦能平臺

PCB聯(lián)盟網(wǎng)

搜索
查看: 4258|回復: 1
收起左側

分享:最新Hotfix_SPB17.20.022_wint_1of1補丁

[復制鏈接]

6

主題

362

帖子

1852

積分

三級會員

Rank: 3Rank: 3

積分
1852
跳轉到指定樓層
樓主
發(fā)表于 2017-6-30 08:36:09 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
Fixed CCRs: SPB 17.2 HF022- `7 h% u2 b9 Q- ]. O: y& B
06-16-2017  o1 T; \5 U5 L: N2 Z! B2 M# b$ n, `* M8 M. E8 g# D. S
========================================================================================================================================================1 ]# S' i; ~$ V0 w+ S; l
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B
% I6 m8 F, t& S========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s
3 {: ^6 j. t# ]& C  _- L1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
8 P/ z2 l1 |( n8 K5 Q; d1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z0 D6 r, p# J6 ~
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
; j6 r8 z1 k6 Q6 {1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager3 f! K! |/ E! d$ C6 r
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications, {: [  k% O1 F# s; g
1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager
" u3 t% B! ~' D: |: |1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X
6 W. c# Q* Z0 X0 G' [; l/ g# [1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B5 c, |5 C! [7 m( p! n
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened
% H( l4 f! W: s$ X5 R1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g# q& z" D, m6 e
1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints9 [* y) }* k4 d, x3 Y! O" Z
1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [
) u4 R7 @. R% h1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k
7 t0 X& R* I/ [; ]1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.) Z) W+ S6 a( w9 D
1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run8 r' D- X. m* V3 S! @9 J; L
1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
' g# V+ x3 o$ b9 V$ d1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @
- B0 g6 w& V' {# K8 ~6 m! k) q: E/ t1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool4 s" W9 f1 @+ _0 }# Y7 R% }2 M
1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s! t5 e/ W) M' `7 ~
1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic' x& [- o. v4 m/ ]
1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P
8 F4 l, f( ~6 m1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
* {; J  X' T/ f. x  o3 ~) e7 i* V1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
/ F/ a( K) `7 R1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h
+ R& w; l  p! J/ s4 f/ v" I5 O4 g1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
+ c4 j) w( z+ g1 M4 f1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly
2 M5 I: b* j$ J' @% W, _1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H! d2 P0 X/ E6 O/ A
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B
( Z) w1 _4 ~7 C( O3 L- ^1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
, @, R9 e2 d) h" n, y8 p1 O1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic2 k5 B* [% n, a. M- t" x
1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j
' M: N6 n% D9 t6 y8 q! l1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
1 \% w1 T/ T1 [) D$ @; D( O6 {1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J3 S4 F  [7 Z9 \/ U0 d
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ], K' i1 _4 N' D5 s) Y2 u
1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \
# K! S  q* R# r  v1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner  ^* c: r3 I% z: h* @; Q/ Y
1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor& _" q- N1 U9 O7 w8 ?& |- K$ F  Z
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
) u4 Q# e1 Z% e1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {- k2 U# s4 q2 l9 F
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O
9 }0 k4 J% c+ c% `6 G. v1 W1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
$ v7 T' O/ K7 r* P7 {7 v" B2 H, b  P( W5 S' Q7 F

% b9 N8 V4 A4 {6 E% @鏈接:http://pan.baidu.com/s/1dFw4emH 密碼:smbg
回復

使用道具 舉報

0

主題

776

帖子

2643

積分

三級會員

Rank: 3Rank: 3

積分
2643
沙發(fā)
發(fā)表于 2022-5-10 09:14:55 | 只看該作者
66666666666666666666666666666666666666- u) Z/ S/ j- T
回復 支持 反對

使用道具 舉報

發(fā)表回復

您需要登錄后才可以回帖 登錄 | 立即注冊

本版積分規(guī)則


聯(lián)系客服 關注微信 下載APP 返回頂部 返回列表